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Byun, Gyungsu

A portrait of Gyungsu Byun



Adjunct Assistant Professor - Lane Department of Computer Science and Electrical Engineering


University of California, Los Angeles, 2010

Dr. Gyungsu Byun received the Ph.D. degree in electrical engineering from the UCLA, Los Angeles, in 2010. Since 2011, he is currently Assistant Professor and Director of the Integrated Circuit and System (ICS) Lab with the Lane CSEE Department of WVU, Morgantown, West Virginia. From 1999 to 2005, he was a Sr. Engineer with Samsung Electronics, where he worked on the design of low power and high speed DRAMs such as DDR2, GDDR3, Rambus and XDR. In 2006, he was a research intern with Intel Corporation where he worked on the design of a cache memory and a 3D chip multi-processor with RISC core architecture. From 2007 to 2011, he was a Sr. Engineer with Inphi Corporation, where he worked on the design of advanced memory buffer, D/PLL, and high speed I/O circuit design between multi-core CPU and DRAM.

Research Focus Areas

Electronic and Photonic Materials and Devices

Research Interests

Low-power Digital Electronics 
Mixed-signal Integrated Circuits and Systems 
Low-power Memory and Microprocessor Architecture

Teaching Interests

Digital Electronics 
Advanced VLSI Design

Special Interests

High-Speed I/O interface 
Digital Delay (or Phase)-Locked Loop and CDR 
CMOS Interface Circuit and System for Wire-Line/Wireless Communication 
Ultra Low-Power Memory Design